Forum Discussion
sstrell
Super Contributor
3 years agoAre you saying this is a parameter set in a standalone IP that you want to transfer into a lower-level (instantiated) Platform Designer system?
Or are you saying this is a component already in a PD system that you want to want to pass its parameter value elsewhere in the system (hierarchical system design)?
- Luigi_Boy3 years ago
New Contributor
Thank you for your reply.
The parameter is set in an IP (4-line SPI) that you can generate with qsys. It's a standalone IP, I'd guess.
My aim is to set this parameter either via a generic that can be generated in 'HDL parameters' (see: https://www.intel.com/content/www/us/en/docs/programmable/683609/21-3/exporting-hdl-parameters-to-a-system.html) or I make this value I set in the given screenshot to other VHDL modules available. It's just to avoid one source for potential mistake.