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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

parameters in schematic editor?

Hi all

I want to make block from verilog file with parameters.

Example:

------------------------------------------

module dff_mod (

d,

clk,

enable,

nrst,

q

);

`define width 18

input [`width-1:0] d;

input clk;

input enable;

input nrst;

output reg [`width-1:0] q;

always @ (posedge clk or negedge nrst)

if(~nrst)

q <= `width'b0;

else

if(enable)

q <= d;

else

q <= `width'b0;

endmodule

--------------------------

I want to make several blocks of dff_mod and use them with different width.

How to do it?? width has to be defined in some special way?

Couldn't find suitable help...

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    I didn' use schematic entry with Quartus since years, but with VHDL coded blocks, generic constant are generally displayed in the schematic editor and can be edited also. The Verilog equivalent to GENERIC isn't `define but parameter syntax, I would expect, parameters from the module definition to be displayed with the block symbol. 

    parameter width = 18;