Forum Discussion
Altera_Forum
Honored Contributor
17 years agoI didn' use schematic entry with Quartus since years, but with VHDL coded blocks, generic constant are generally displayed in the schematic editor and can be edited also. The Verilog equivalent to GENERIC isn't `define but parameter syntax, I would expect, parameters from the module definition to be displayed with the block symbol.
parameter width = 18;