Altera_Forum
Honored Contributor
15 years agoOutput pins stuck at VCC or Ground. No idea why
I have found many posts about this but havent found a solution. Both my friend and I are having issues with this. I'll post my code on pastebin as it is 500 lines long, most of it is repeated, so it really isn't too complex.
When I compile the block diagram it says that every output pin is stuck at vcc or ground and the every input pin doesnt drive logic. I also get these 2 errors: -Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family -Warning: No paths found for timing analysis ***MAKE SURE TO REMOVE THE SPACES AND * BETWEEN COM IN THE URL*** Here's the pastebin code. pastebin. * c * o * m/YtPg8H5j Here's a picture of the schematic: i27.photobucket. * c * o * m/albums/c198/swargy/Random/design.png?t=1292047094 Any help would be greatly appreciated. Thanks!