Honored ContributorHey, I have this code, compiled on the Cyclone II, and it keeps giving me warnings about the output pins being stuck at VCC or GND.
When I tried testing it in Modelsim, it gave me tons of errors about the procedures not being able to drive the output signals. and yes, I did just post in another OLD thread about this, but forgot to comment my code.
Honored ContributorJust had a quick glance at your code. It is clear you are following software mindset of sequential actions.
HDL does not work like that. HDL is made up of parallel (concurrent assignments) except inside sequential bodies. HDL sequential assignments are not translated directly to sequential hardware. instead, at compile time they are resolved (inferred) to a logic (comb or seq) parallel with your other assignments. Thus the order of parallel statements is irrelevant unlike software but the order of seq assignments within one seq body matters at compile time... Notice for example: process a <= '0'; a <= '1'; a <= '0'; end process; is resolved as you want a <= '0' according to the last statement overwriting unconditionally. also notice your delay procedure is doing nothing and no delay is inferred.Honored ContributorFirst off, my delay circuit is just supposed to be an empty for loop that just runs through.
Second, what would you recommend concerning the tasks I must do sequentially in order for this to work on the Cyclone 2?Honored Contributorshoot, gave the wrong file.
Here it is
