Output pins stuck at VCC or GND??

Just had a quick glance at your code. It is clear you are following software mindset of sequential actions.

HDL does not work like that. HDL is made up of parallel (concurrent assignments) except inside sequential bodies. HDL sequential assignments are not translated directly to sequential hardware. instead, at compile time they are resolved (inferred) to a logic (comb or seq) parallel with your other assignments. Thus the order of parallel statements is irrelevant unlike software but the order of seq assignments within one seq body matters at compile time...

Notice for example:

process

a <= '0';

a <= '1';

a <= '0';

end process;

is resolved as you want a <= '0' according to the last statement overwriting unconditionally.

also notice your delay procedure is doing nothing and no delay is inferred.