Honored ContributorHi all,
I have a counter that counts up every time an input of '1' is seen. At the max count value a flag should output '1' and the count resets. I can achieve this, however the output lasts for as long as the input stays at '1' on the final count. How do you code for an output to last for just one clock cycle? Thanks
Honored ContributorHonored ContributorI'm in work and its on my laptop, let me type it over.
Honored Contributorhere:
process begin if reset = '1' then count <= 0; elsif rising_edge (clk) then if count < 255 then if input = '1' then count <= count + 1; end if; end if; end;Honored Contributoryou are asking your count to stay at 255 once it reaches there and where is the output?
Honored Contributorsorry, second process is:
process begin if count = 255 then flag <= '1'; else flag = '0'; end if; end;Honored Contributorwell comment out that if count < 255 and its fellow end if. then if your counter is 8 bits it will move back to zero by itself on enable (or on reset)
Honored ContributorThanks, I removed that, it made no difference to the simulation at all. When input stays '1' the output changes every +ve clk edge. I need the output to only change once for each time the input goes '1', then change again when the input next goes '1' again (after it has been '0').
Honored Contributornow your requirement changed. You want input 0=>1 to enable count and not just 1 so you need to redesign your counter on that basis.
inside process: input_d <= input; if input = '1' and input_d = '0' then count <= count + 1; ...Honored ContributorCheers,
got to get back to work but i'll give it a shot later and get back to you.Honored ContributorCouldn't get this to work, heres my code in full. Sorry if I confused the question. What happens is that whenever on_input = '1' then the count increases every time the clk goes +ve. I require it to count up only once no mater how long the on_input is held at '1'. I can see why the design I have operates as it does, but I can't work out how to change it to what I need. I need the overflow to act in a similar way. Thanks.
entity counter is port (clk : in std_logic; on_input : in std_logic; reset : in std_logic; overflow : out std_logic; values : out integer range 0 to 255); end counter; architecture Behavioral of counter is signal count : integer range 0 to 255; begin counter_process : process (clk, reset, on_input) begin if reset = '1' then count <= 0; elsif rising_edge (clk) and on_input = '1' then if count < 255 then count <= count + 1; end if; else count <= count; end if; end process counter_process; overflow_process : process (count) begin if count > 255 then overflow <= '1'; else overflow <= '0'; end if; end process overflow_process; values <= count; end Behavioral;
