Output for only one clock cycle

Couldn't get this to work, heres my code in full. Sorry if I confused the question. What happens is that whenever on_input = '1' then the count increases every time the clk goes +ve. I require it to count up only once no mater how long the on_input is held at '1'. I can see why the design I have operates as it does, but I can't work out how to change it to what I need. I need the overflow to act in a similar way. Thanks.

entity counter is

port (clk : in std_logic;

on_input : in std_logic;

reset : in std_logic;

overflow : out std_logic;

values : out integer range 0 to 255);

end counter;

architecture Behavioral of counter is

signal count : integer range 0 to 255;

begin

counter_process : process (clk, reset, on_input)

begin

if reset = '1' then count <= 0;

elsif rising_edge (clk) and on_input = '1' then

if count < 255 then

count <= count + 1;

end if;

else count <= count;

end if;

end process counter_process;

overflow_process : process (count)

begin

if count > 255 then overflow <= '1';

else overflow <= '0';

end if;

end process overflow_process;

values <= count;

end Behavioral;