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I dont really understand, from your description, what the problem is. If something isnt toggling then the usualy debug is to trace the signal back until you find the source of the problem.
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Hi, sorry I didn't make myself clear the first time I posted (by the way, I don't see the content of my post, just the title), the problem is that just a single output from a stand alone working module stops toggling when added to a test bench, and the fix is to assign that output to another signal at the same time that is supposed to toggle.
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As a side note - You would probably be better off driving the design from the testbench rather than force from a .do file. Are you sure the paths here are correct? have they changed at all between original verilog and vhdl top level? Force is really only for overriding a value already set in a test.
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The paths are correct and everything is working, I'm using a test bench, the do file was using for testing the module as a stand alone unit.
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