Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

output doesn't toggle when simulating with other entities in Modelsim

Hi, I'm working on a vhdl testbench to simulate the behaviour of an I2C bus. I started with an original code (written in verilog) that works, made some changes to it an simulate it's behaviour as a s...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

I dont really understand, from your description, what the problem is. If something isnt toggling then the usualy debug is to trace the signal back until you find the source of the problem.

As a side note - You would probably be better off driving the design from the testbench rather than force from a .do file. Are you sure the paths here are correct? have they changed at all between original verilog and vhdl top level? Force is really only for overriding a value already set in a test.