Ok, but I fail to see how the exact encoding value for each operation matters, given the way FPGAs work.
Are you using a prioritized case statement to generate the logic, or is it a purely logical operation?
Without seeing the code you write it is hard to make any substantial comment on the result you see.
Examples (in verilog):
reg [7:0] a;
reg [7:0] b;
reg [7:0] s;
reg [1:0] f;
// unordered:
s = ({8{f==0}} & (a+b)) | ({8{f==1}} & (a-b)) | ({8{f==2}} & (a|b)) | ({8{f==3}} & (a&b));
case (f)
0: s = a+b;
1: s = a-b;
2: s = a|b;
3: s = a&b;
endcase
// prioritized/ordered:
s = (f == 0) ? (a+b) : ((f == 1) ? (a-b) : (((f == 2) ? (a|b) : (a&b))));
if (f == 0) s = a+b;
else if (f == 1) s = a-b;
else if (f == 2 ) s = a|b;
else s = a&b;