Opposite logic of work

Question

I'm using this board (ALTERA-CoreEP4CE6-EP4CE6E22C8N). I followed the example. The problem is that contrary to the description of the example, the behavior is the opposite of what is written.

Actual Block diagram (Quartus Prime Lite 22.1.1):

So, when starting, the key[0] and key[1] buttons are not pressed on the board and led[0], led[2], led[3], led[5] should be lit, because pins 86 and 87 are in logical "1", since they have a Weak Pull-Up Resistor (On). 
But led[1] and led[4] really glow! In this case, inst5 (AND2) behaves likeOR2, inst6 (OR2) behaves like AND2, inst7 (XOR) behaves like XOR+NOT !!! What's happening?! 
I will not write further, because the logic already contradicts the explicit scheme. The impression is that the Weak Pull-Up Resistor (On) setting in the Assigment Editor has no effect, and pins 86 and 87 are "dangling in the air." Although the "Cyclone IV Device Datasheet" says "All I/O pins have an option to enable weak pull-up except the configuration, test, and JTAG pins."  But that's not all, it doesn't explain the behavior inst5, inst6, inst7 even with this assumption.
I'm stuck at this moment. Tell me please, what is the solution to the problem? Thanks for your help!
Actual Assigment editor (Quartus Prime Lite 22.1.1):

P.S.
On the block diagram, states 0 and 1 show the actual state of the leds of the working board, respectively, the state of key[0] (red) OR key[1] (blue), as well as key[0] AND key[1] (black). The project was tested in three versions of Quartus Prime Lite Edition - 17.1, 22.1, 22.1.1 - there are no compilation errors, the project behavior on the board is the same. 
The project is written to the FPGA RAM, after the power is restarted, the test project "running led[0] - led[7]" from ROM is normally launched, that is, its logic corresponds to the factory one.

sstrell · Answer

Not sure why you are using weak pull-ups on inputs.  They're usually used on outputs so it's possible that assignment has no effect but...
Also remember that LEDs are usually active low.  So leds 1 and 4 being on is not surprising.

richardt_altera · Answer

This may be related to the following knowledge article, which discusses the enabling of weak pull-up after power-up. https://www.intel.com/content/www/us/en/support/programmable/articles/000085785.html

Best Regards,

Richard Tan

richardt_altera · Answer

Dropping a note to ask if my last reply was helpful to you?Do you need any further assistance from my side? Best Regards,Richard Tan

serg4 · Answer

Thank you very much for your response. It is useful to me, I didn't know that.

serg4 · Answer

Thanks for your answer. I applied resistors on the input so that the inputs to which the buttons are connected do not float in the air in an indeterminate state when the buttons are in the default unpressed state. So it says in many training materials with example projects based on ready-made training FPGA boards, you probably missed or forgot this material?
According to this example, the buttons are in an unpressed state at startup. One end of buttons are grounded, second commutate to input of FPGA. But at the same time, the FPGA inputs to which these buttons are switched, are in logical "1" due to weak pull-up resistors, and the logic of the circuit must proceed from the this starting operating conditions, when there are clear logical "1" on both FPGA inputs. I see a completely different logic of work, that's why I asked the question.

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Opposite logic of work

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