Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Operating the LVDS transceivers at top speeds

At least the Arria GX family is announced as providing multiple 3.125 GBit links. As it seems, these speeds are not readily accessible. The ALTLVDS component somehow doesn't provide a combination of parameters to reach anything above 1 GBit.

Of course, the deserialization factor has to be 10 as this factor is the clock multiplicator of the parallel to serial converter. With the 10bit shift register and 312.5MHz on the parallel queue, and 3.125GHz on the Serial, there should be 3.125GBit available on the output.

Or is the ALTLVDS the wrong component to accomplish this ?

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Indeed, wrong component.

    The ALTLVDS function is for normal I/Os, which can only achieve ~840 Mbps.

    To achieve higher speed, you need to use the transceivers, via the ALTGXB function.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Hmm, maybe the correct module name is ATL2GXB or ALTGX.

    BTW, which version of Quartus are you using?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Thanks. I was able to configure the ALT2GBX component. and the Pinplaner for Arria GX is there while the Pinplaner for Cyclone4 is missing.

    I'm using Quartus2 Version 9.1, the last one to support schematic entry and waveform simulation.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    The Cyclone4-E doesn't have the high speed transceivers, it seems. They end at 840MBit. The Cyclone4-GX with 8 channels is already providing up to 3.125GBit. We need the high speed transceivers to generate nanosecond and sub nanosecond pulse pattern for physical experiments. So the whole protocol stuff is to be bypassed, the required FPGA internal functionality is simple, read out a RAM, and let an attached 32bit processor fill the RAM. Meaning a 64 pin case would be sufficient, now we are at 760 pins.