Operating the LVDS transceivers at top speeds

The Cyclone4-E doesn't have the high speed transceivers, it seems. They end at 840MBit. The Cyclone4-GX with 8 channels is already providing up to 3.125GBit. We need the high speed transceivers to generate nanosecond and sub nanosecond pulse pattern for physical experiments. So the whole protocol stuff is to be bypassed, the required FPGA internal functionality is simple, read out a RAM, and let an attached 32bit processor fill the RAM. Meaning a 64 pin case would be sufficient, now we are at 760 pins.