OpenCL kernel takes more than 36 hours to compile on Arria 10

Yes, the resource estimation can be significantly off. However, if a resource is overutilized, the process will fail during fitting with a clear error message. The only cases I have seen where placement and routing continues forever is if the design narrowly fits on the FPGA, but the routing never succeeds and keeps retrying to no avail. Can you sort the files generated by the compiler based on time and tell me what is the last file that follows the pattern of top.X.summary (X: map, merge, fit, flow, sta)?