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I am unfamiliar with the protocol, but at first glance it seems all right, but for the clk_count_write variable. You use this without initialisation.
And another point, why do you choose your state machine to be fully clock dependent? I was tought to make a combinatorial state machine, but to handle the state assignment under a clock edge.
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clk_count_write is defined as an integer range 0 to 183, therefore it initialises to 0. All signals/variables initialise to their leftmost value, unless specified otherwise, hence why std_logic always defaults to 'U'.
A single process state machine is definiately the way to go. The 2 process method can be prone to errors when engineers forget signals in the sentivity lists, or forget to assign signals in every case. So for most people the single process (under a single clock as you put it) is a very very good idea. With a single process you only need clk (and maybe reset) in the sensitivity list, and every output is registered, so you are not going to get missmatches between simulation and the hardware, and no latches can be created inadvertently.
To the OP: I dont know enough about single wire interface. But from your code, you didnt post a testbench. How does it work in simulation? can you recreate the problems in a simulation to help debug the problem?
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