Honored ContributorHello everyone, how many number of clock cycle will be consumed by division function offred by Quartus II to produce the result ? My input data width are 16 bit.
Honored ContributorI don't know, but you could create it an measure. either in simulation or in implementation.
Honored Contributoractually i dont have quartus software. I have xilinx ISE Design Suite. So i want to know about this before switching to Quartus II
Honored ContributorAre you using a Xilinx Chip? or are you moving to altera chips?
Either way - you can just generate a divider core with a pipeline that should be configurable. You could set the number of clocks to 1 if you like. But usually, with 1 clock pipeline, the fmax would be so slow that you'll actually be able to compute values quicker with larger pipeline length.Honored ContributorYou can also simulate your design in Modelsim Altera Starter edition which is free to check on the clock cycle.
Honored Contributorif you have 16 bit width number and do division we assume you use the most fast division in most cases it is shift operation only.
After shifting you can correct your result according to remainder.Honored Contributorbut for 16 bit its taking 16 clock cycle
Honored Contributorthat number of clocks it takes should be a parameter of the divider core when you generated the core.
Honored Contributoris there any other way for division operation in minimum number of cycle?
Honored ContributorYes- generate a new divider core.
Honored ContributorSir, can you explain it please?
