Number of clock cycle consumed by division function offred by Quartus II ?

Are you using a Xilinx Chip? or are you moving to altera chips?

Either way - you can just generate a divider core with a pipeline that should be configurable. You could set the number of clocks to 1 if you like. But usually, with 1 clock pipeline, the fmax would be so slow that you'll actually be able to compute values quicker with larger pipeline length.