New Contributor
Super ContributorHi @emaferna
The IE happened in the flow converting inferred RAMs back to logic due to asynchronous read logic and unregistered RAM output.
Engineering able to rewrite the design in a way that passes synthesis. Attached the .qar. The main changes can be found in the screenshot below.
The original design defined a true dual port RAM, but the two read ports (corresponding to ssd1_reg and ssd2_reg) are actually reading the same address, so it can be reduced to a simple dual port RAM.
hex_to_ssd and setting of output value to "1111110" are moved to be performed on the registered RAM output rather than the direct RAM output, preserving what is defined in the original design.
Best Regards,
Richard Tan
p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.
Super ContributorHi @emaferna
I have yet to receive any response from you to the previous question/reply/answer that I have provided but I believed that I have answered your question.
With that, I will now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.
Best Regards,
Richard Tan
p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.
