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ntel Software: Quartus Prime Lite 20.1 Internal Error: Sub-system: CDB_SGATE
Hello to everyone, I am using a simple VHDL code in which I have a function defined into architecture's declarative part, but during Analysis and Synthesis, Quartus gives me the following "Quartus Prime software report" : Problem Details Error: Internal Error: Sub-system: CDB_SGATE, File: /quartus/db/cdb_sgate/cdb_sgate_sys.cpp, Line: 3420 iterm != 0 Stack Trace: 0x5bef2: CDB_SGATE_OTERM::insert_fanout + 0x43bd2 (db_cdb_sgate) 0x14bd9: OPT_RAM_POTENTIAL_CANDIDATE::create_true_dual_port_ram_bit_dff + 0x7a9 (SYNTH_INFER) 0xbe1e: OPT_RAM_INFERENCE::create_ram_bits + 0x41e (SYNTH_INFER) 0xa68b: OPT_RAM_INFERENCE::convert_synchronous_ram_sgate_to_nodes + 0xb9b (SYNTH_INFER) 0x9a4b: OPT_RAM_INFERENCE::convert_ram_nodes + 0x4cb (SYNTH_INFER) 0x37278: RTL_SCRIPT::call_ram_rom_fns + 0x220 (SYNTH_OPT) 0x34987: RTL_SCRIPT::call_named_function + 0x597 (SYNTH_OPT) 0x33a08: RTL_SCRIPT::process_script + 0x52c (SYNTH_OPT) 0x33013: opt_process_netlist_scripted + 0x7df (SYNTH_OPT) 0x3a1fa: RTL_ROOT::process_sgate_netlist + 0x1aa (SYNTH_OPT) 0x15d728: SGN_SYNTHESIS::high_level_synthesis + 0x198 (synth_sgn) 0x15e132: SGN_SYNTHESIS::process_current_stage + 0x222 (synth_sgn) 0xc75d5: SGN_EXTRACTOR::synthesize_partition + 0x195 (synth_sgn) 0xc71bf: SGN_EXTRACTOR::synthesis + 0x20f (synth_sgn) 0xc7334: SGN_EXTRACTOR::synthesis_and_post_processing + 0xc4 (synth_sgn) 0x13303: sgn_qic_full + 0x2a3 (synth_sgn) 0x43af: qsyn_execute_sgn + 0x13f (quartus_map) 0x14246: QSYN_FRAMEWORK::execute_core + 0x136 (quartus_map) 0x13d2b: QSYN_FRAMEWORK::execute + 0x49b (quartus_map) 0x1150c: qexe_do_normal + 0x1ec (comp_qexe) 0x16622: qexe_run + 0x432 (comp_qexe) 0x17371: qexe_standard_main + 0xc1 (comp_qexe) 0x1b42b: qsyn_main + 0x53b (quartus_map) 0x13258: msg_main_thread + 0x18 (CCL_MSG) 0x14a5e: msg_thread_wrapper + 0x6e (CCL_MSG) 0x16af0: mem_thread_wrapper + 0x70 (ccl_mem) 0x12af1: msg_exe_main + 0xa1 (CCL_MSG) 0x2a236: __tmainCRTStartup + 0x10e (quartus_map) 0x14033: BaseThreadInitThunk + 0x13 (KERNEL32) 0x73690: RtlUserThreadStart + 0x20 (ntdll) End-trace Executable: quartus_map Comment: None System Information Platform: windows64 OS name: Windows 10 OS version: 10.0 Quartus Prime Information Address bits: 64 Version: 20.1.1 Build: 720 Edition: Lite Edition In attechment I have put the archived project. I did a support service request, but I was adressed here in the Community. Is there someone that can help me to undertand the reason and how to resolve it? Thank you in advance.1.9KViews0likes3CommentsRe: Reusing components: basics
Hello, what I was trying to do I had already highlighted with my pdf attachment. The question remains open whether it is possible to create pre-compiled user libraries that can be referenced in QUARTUS, as it can be done in MODELSIM. Kind regards2.8KViews0likes1CommentRe: Reusing components: basics
Hello, I solved it by entering the paths of the source files of each respective project using: Setting-Files-Add Source files are used during compilation, referencing them and not copying them. Question: but there is no way to create a compiled library from QUARTUS and not MODELSIM to be reused?2.9KViews0likes1CommentReusing components: basics
Hello, using QUARTUS PRIME (LITE EDITION): I wrote and tested an easy myAND2 basic project in a folder "progetto_myAND2". I wrote and tested an easy myOR2 basic project in a folder "progetto_myOR2". Then, I wrote an easy myCIRCUIT project in a folder "progetto_myCIRCUT" as a netlist. Each project have its proper folder. I wolud like to reuse, as components, myAND2 and myOR2 in myCIRCUIT. I did understand yet how to tell Quartus of reference the entity done in the two previous projects. Can you help to understand how to set QUARTUS in order to do that? In attachment I put vhdl code and errors from compiler. Thank you in advance2.9KViews0likes5CommentsVHDL Quartus Simulation, Libraries and Packages
Hello, I have: an entity that implements a circuit for parity check: it have as input an 8 bit std_logic_vector and an std_logic as output. It is located in the folder: C:\User\Desktop\Conversioni_di_Tipo\ParityChecker\ParityChecker.vhd a function that converts a char in an 8 bit standard_logic_vector, defined in a package, located in the folder: C:\Users\Desktop\Conversioni_di_Tipo\myLibrary_1\ema_conversion_pkg.vhd a testbench which have that entity as DUT but that also uses the conversion function in the package. It is located in the folder: C:\Users\Desktop\Conversioni_di_Tipo\ParityChecker\simulation\modelsim\ParityChecker_tb.vhd The Quartus project is located in the folder: C:\Users\\Desktop\Conversioni_di_Tipo\ParityChecker The file added to the project is the ParityChecker.vhd (it is obviously the top-level entity). The simulator is ModelSim-Altera. The testbench file ParityChecker_tb.vhd is set in Assegniment --> Setting --> Simulation --> TestBenches... I start the Analysis & Elaboration that go correctly to the end. Then, I start RTL simulation, ModelSim open but an it gives these errors because it doesn’t find the package. # Reading pref.tcl # do ParityChecker_run_msim_rtl_vhdl.do # if {[file exists rtl_work]} { # vdel -lib rtl_work -all # } # vlib rtl_work # vmap work rtl_work # Model Technology ModelSim - Intel FPGA Edition vmap 2020.1 Lib Mapping Utility 2020.02 Feb 28 2020 # vmap work rtl_work # Copying C:/intelFPGA_lite/20.1/modelsim_ase/win32aloem/../modelsim.ini to modelsim.ini # Modifying modelsim.ini # # vcom -93 -work work {C:/Users//Desktop/Conversioni_di_Tipo/ParityChecker/ParityChecker.vhd} # Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020 # Start time: 17:36:37 on Nov 18,2020 # vcom -reportprogress 300 -93 -work work C:/Users//Desktop/Conversioni_di_Tipo/ParityChecker/ParityChecker.vhd # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Compiling entity ParityChecker # -- Compiling architecture Behavioral of ParityChecker # End time: 17:36:38 on Nov 18,2020, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # # vcom -93 -work work {C:/Users/Desktop/Conversioni_di_Tipo/ParityChecker/simulation/modelsim/ParityChecker_TB.vhd} # Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020 # Start time: 17:36:40 on Nov 18,2020 # vcom -reportprogress 300 -93 -work work C:/Users/Desktop/Conversioni_di_Tipo/ParityChecker/simulation/modelsim/ParityChecker_TB.vhd # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # ** Error: C:/Users/Desktop/Conversioni_di_Tipo/ParityChecker/simulation/modelsim/ParityChecker_TB.vhd(5): (vcom-1598) Library "mylibrary_1" not found. # ** Error: C:/Users/Desktop/Conversioni_di_Tipo/ParityChecker/simulation/modelsim/ParityChecker_TB.vhd(6): (vcom-1136) Unknown identifier "myLibrary_1". # ** Note: C:/Users/Desktop/Conversioni_di_Tipo/ParityChecker/simulation/modelsim/ParityChecker_TB.vhd(8): VHDL Compiler exiting # End time: 17:36:40 on Nov 18,2020, Elapsed time: 0:00:00 # Errors: 2, Warnings: 0 # ** Error: C:/intelFPGA_lite/20.1/modelsim_ase/win32aloem/vcom failed. # Error in macro ./ParityChecker_run_msim_rtl_vhdl.do line 10 # C:/intelFPGA_lite/20.1/modelsim_ase/win32aloem/vcom failed. # while executing # "vcom -93 -work work {C:/Users/Desktop/Conversioni_di_Tipo/ParityChecker/simulation/modelsim/ParityChecker_TB.vhd}" Could you help me to understand how the libraries have to be handle in a corret manner, especially when user file (needed in a simulation) are arbitrarly located in the PC? Thank you. Here you can see the file discussed above. ---------------------------------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ----------------------------------------------------- ENTITY ParityChecker IS GENERIC (oddParity: STD_LOGIC := '1'); -- ='1' per rilevare la parità dISpari PORT ( x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); y : OUT STD_LOGIC); END ParityChecker; ARCHITECTURE Behavioral OF ParityChecker IS BEGIN PROCESS (x) IS VARIABLE y_var: STD_LOGIC; begIN y_var := NOT(oddParity); for i IN x'RANGE LOOP y_var := y_var XOR x(i); END LOOP; y <= y_var; END PROCESS; END Behavioral; ---------------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; ------------------------------------------------ package ema_conversions_pkg is function char_to_slv (signal charIN: character; constant bitwidth: natural) return std_logic_vector; end package ema_conversions_pkg; ------------------------------------------------ package body ema_conversions_pkg is function char_to_slv (signal charIN: character; constant bitwidth: natural) return std_logic_vector is begin return std_logic_vector(to_unsigned(CHARACTER'POS(charIN), bitwidth)); end function char_to_slv; end package body ema_conversions_pkg; ---------------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all; library myLibrary_1; use myLibrary_1.ema_conversions_pkg.all; ---------------------------------------------------------------------------------- entity ParityChecker_TB is end ParityChecker_TB; ---------------------------------------------------------------------------------- architecture Behavioral of ParityChecker_TB is signal y_tb: std_logic; signal charIN: character; signal x_tb: std_logic_vector(7 downto 0); begin x_tb <= char_to_slv(charIN,8); DUT: entity work.ParityChecker generic map('1') -- ='1' per rilevare la parità dispari, ='0' per rilevare la parità pari port map(x_tb, y_tb); STIM: process is begin charIN <= 'a'; wait for 20 ns; charIN <= 'c'; wait for 20 ns; charIN <= 'F'; wait; end process; end Behavioral; ----------------------------------------------------------------------------------------------------------1.1KViews0likes1CommentRe: VHDL Configuration for TestBenches Issue
Hi, Thanks for the reply. What I tried to do was to run the testbench by setting up the mytestbench.vhd file in Quartus: Setting -> Simulation -> Compile test bench ... In this way the simulation started but ModelSim ignored the configuration declaration present in the file mytestbench.vhd; to run the simulation on the configuration I should: 1) stop the simulation that has opened 2) go to the configuration design unit, in the Library tab, 3) right-click on it and launch the simulation (it seems to me that it is also the equivalent of the command you gave me). 4) then see the signals of interest The point is that I tried from within Quartus but I failed, as ModelSim seems to implement the default binding on the testbench it reads from Quartus anyway. So I also tried to comment out the configuration declaration in the mytestbench.vhd file and create a new file containing only the configuration declaration, mytestconfig.vhd, (leaving untouched the mytestbench.vhd file in the same folder), and thus put the file mytestconfig.vhd in Quartus: Setting -> Simulation -> Compile test bench ... However, when running the simulation, the simulator gave me an error. It seems that in order to simulate a configuration you have to do it from ModelSim, as indicated previously. I wonder if, acting from inside Quartus, it is possible to choose the configuration to simulate. Thank you.1.9KViews0likes0CommentsRe: VHDL Configuration for TestBenches Issue
Sorry, I did a syntax error in the previus post: the architecture in the configuration is test1. This error was made only in writing the post, not in the running vhdl code. ------------------------------------------------------- configuration Tester of TestBench is for test1 for gateTst1 : device1 use entity WORK.myAnd2(ex1) port map (x => a, y => b, z => c); end for; end for; end configuration Tester; ---------------------------------------------------------1.9KViews0likes0CommentsVHDL Configuration for TestBenches Issue
Hello, I have a very simple entity (an AND 2 input gate) named myAnd2 with an architecture (named ex1), as top level design unit. I also have a testbench with two architecture (named test1, test2) , set for ModelSim-Altera simulator. Finally, I have a configuration declaration at the testbench file unit.. I was wonder why simulator always executes the last architecture described (named "test2") instead of executing what is indicated in the configuration declaration. Someone of you can help me? Thanks. --------------------------------------------------------- entity TestBench is end entity TestBench; --------------------------------------------------------- architecture test1 of TestBench is component device1 is port (x, y : in STD_LOGIC; z: out STD_LOGIC); end component device1; begin gateTst1: device1 port map (x => a, y => b, z => c); ... end architecture test1; --------------------------------------------------------- architecture test2 of TestBench is component device2 is port (x, y : in STD_LOGIC; z: out STD_LOGIC); end component device2; begin gateTst2: device2 port map (x => a, y => b, z => c); ... end architecture test2; ------------------------------------------------------- configuration Tester of TestBench is for io for gateTst1 : device1 use entity WORK.myAnd2(ex1) port map (x => a, y => b, z => c); end for; end for; end configuration Tester; ---------------------------------------------------------1.9KViews0likes4CommentsVHDL Configuration Specification and Functional Simulation
Hello to everyone, I have: *) an entity (a trivial and 2-input) with 3 architectures *) a configuration specification (at the end of the entity file itself, in which specific for the entity to use architecture 2. *) a test bench performed in ModelSim-Altera I can't make the configuration effective, as the last architecture described is always simulated. How do I make a configuration other than the default one take effect? Could some of you give me a small working example, or tell me how to do it properly? Thanks. Here the code of the top file: -------------------------------------------- library ieee; use ieee.std_logic_1164.all; -------------------------------------------- entity my_and2 is generic (delay: DELAY_LENGTH: = 5 ns); port ( x, y: in STD_LOGIC; z: out STD_LOGIC ); end entity my_and2; -------------------------------------------- - architecture with a delay of 5 ns architecture arch1 of my_and2 is begin z <= x and y after delay; end architecture arch1; -------------------------------------------- - architecture with delay of 10 ns architecture arch2 of my_and2 is begin z <= x and y after 10 ns; end architecture arch2; -------------------------------------------- - architecture without delay architecture arch3 of my_and2 is signal xy: STD_LOGIC_VECTOR (0 to 1); begin xy <= x & y; with xy select z <= '1' when "11", '0' when others; end architecture arch3; ---------------------------------------------- - configuration And2Config of my_and2 is for arch2 end for; end configuration And2Config; - ---------------------------------------------- Here the code of the Test bench file: ---------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY tb IS END tb; ARCHITECTURE tb_arch OF tb IS - constants - signals SIGNAL x: STD_LOGIC; SIGNAL y: STD_LOGIC; SIGNAL z: STD_LOGIC; COMPONENT my_and2 PORT ( x: IN STD_LOGIC; y: IN STD_LOGIC; z: OUT STD_LOGIC ); END COMPONENT; BEGIN i1: my_and2 PORT MAP ( - list connections between master ports and signals x => x, y => y, z => z ); - x t_prcs_x: PROCESS BEGIN x <= '0'; WAIT FOR 220000 ps; x <= '1'; WAIT FOR 200000 ps; x <= '0'; WAIT; END PROCESS t_prcs_x; - y t_prcs_y: PROCESS BEGIN y <= '0'; WAIT FOR 290000 ps; y <= '1'; WAIT FOR 430000 ps; y <= '0'; WAIT; END PROCESS t_prcs_y; END tb_arch; ----------------------------------------------1.2KViews0likes2Comments