Forum Discussion
Pooja_03
New Contributor
1 year agoNot able to get the 3.3V peak to peak from PLL generated output signal
Hi, I have generated a PLL (ALTPLL) IP in Quartus Lite software for the MAX10 FPGA (10M50DAF484C6GES). In the IP configuration, I set the input frequency to 50 MHz and generated an output frequency ...
AqidAyman_Altera
Regular Contributor
1 year agoI hope the previous response was sufficient to help you proceed. As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.