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Pooja_03's avatar
Pooja_03
Icon for New Contributor rankNew Contributor
1 year ago

Not able to get the 3.3V peak to peak from PLL generated output signal

Hi, I have generated a PLL (ALTPLL) IP in Quartus Lite software for the MAX10 FPGA (10M50DAF484C6GES). In the IP configuration, I set the input frequency to 50 MHz and generated an output frequency ...
Hdl
AqidAyman_Altera's avatar
AqidAyman_Altera
Icon for Regular Contributor rankRegular Contributor
1 year ago

Hello,


I wish to follow up, with the answer provided, do you have any more questions on this?


Regards,

Aqid