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Pooja_03's avatar
Pooja_03
Icon for New Contributor rankNew Contributor
1 year ago

Not able to get the 3.3V peak to peak from PLL generated output signal

Hi, I have generated a PLL (ALTPLL) IP in Quartus Lite software for the MAX10 FPGA (10M50DAF484C6GES). In the IP configuration, I set the input frequency to 50 MHz and generated an output frequency ...
Hdl
FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
1 year ago

Hi,

most likely an oscilloscope and probing problem. Depending on oscilloscope and probe parameters, you won't necessarily reproduce 3.3V square wave exactly.
Please give details about used oscilloscope and probe, also possible bandwidth reduction in oscilloscope channel setup.
Which GPIO pin are you using, is there anything else connected to it except for the oscilloscope input?