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Altera_Forum's avatar
Altera_Forum
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12 years ago

Non-positive replication multiplier inside concat

Hi,recently I am focusing on a MSK IQ demodulating.

after synthesize with Q2.9.1 and Pro Synplify.9.6.2,there come the warnings as following:

# ** Warning: (vsim-8607) D:/altera/91/quartus/eda/sim_lib/cycloneii_atoms.v(6831): Non-positive replication multiplier inside concat. Replication will be ignored.# ** Warning: (vsim-8607) D:/altera/91/quartus/eda/sim_lib/cycloneii_atoms.v(6832): Non-positive replication multiplier inside concat. Replication will be ignored.# ** Warning: (vsim-8607) D:/altera/91/quartus/eda/sim_lib/cycloneii_atoms.v(6831): Non-positive replication multiplier inside concat. Replication will be ignored.# ** Warning: (vsim-8607) D:/altera/91/quartus/eda/sim_lib/cycloneii_atoms.v(6832): Non-positive replication multiplier inside concat. Replication will be ignored.

first i google it finding some similar prblem posted by others.

but the difference lies my warnings show in Altera EDA sim_lib cycloneii_atoms.v while others' shows in verilog composed by themselvs,

so i dont know how to figure it out.

The signal is Hi-Z value with Red line in Wave_window.

I have neve encounted pronlems like this,plz someone help me out.

bye the way,currently i have to use a Lut-reg based multipier instead of DSP embedded mult....there is no problems in wave_window when use a lut-reg way--||||

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    Usually a problem of data and coefficient word widths. If they are not well considered, some result bits might be undriven. 'Z' state can only occur, if you are driving an inout port, respectively a signal vector intentionally initialized to 'Z'.

    In simulation, you should be always able to locate the "source" of undriven signals.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    --- Quote Start ---

    Usually a problem of data and coefficient word widths. If they are not well considered, some result bits might be undriven. 'Z' state can only occur, if you are driving an inout port, respectively a signal vector intentionally initialized to 'Z'.

    In simulation, you should be always able to locate the "source" of undriven signals.

    --- Quote End ---

    Yeah,following your tips,I did check my whole sources several times and found some uninitialized registers.

    After fixments in functional Sim,there's no warning or hi-z any more,but in post-sim the Hi-z still exists.

    In my project,I write a PN generator in verilog format to activate MSK_modulator.vo,and then in top testbench i instance them both.

    I got a question if the mixed way simulation(.v/.vo exist in top at the same time) can called post-sim,can it result in the "undirven" to vo file?

    thx all the way