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Usually a problem of data and coefficient word widths. If they are not well considered, some result bits might be undriven. 'Z' state can only occur, if you are driving an inout port, respectively a signal vector intentionally initialized to 'Z'.
In simulation, you should be always able to locate the "source" of undriven signals.
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Yeah,following your tips,I did check my whole sources several times and found some uninitialized registers.
After fixments in functional Sim,there's no warning or hi-z any more,but in post-sim the Hi-z still exists.
In my project,I write a PN generator in verilog format to activate MSK_modulator.vo,and then in top testbench i instance them both.
I got a question if the mixed way simulation(.v/.vo exist in top at the same time) can called post-sim,can it result in the "undirven" to vo file?
thx all the way
Honored Contributor
