Node * determined to be a clock

looking at this, it looks like you may have created a clock by actually clocking some logic using the change in state of the state machine. Any chance of posting some code?

Hi

-- SRAM
--============================================================================================================================     
    nCE<='0';
    nLB<='0';
    nUB<='0';
   ----------------------------------------------------------
    mem <= '1' WHEN wrusedw_fv<100 ELSE
             '0';
    rw <=  '0';
    ---------------------------------------------------------- SRAM CONTROLER STATE MACHINE
        next_state <=     r1 WHEN current_state=idle and mem='1' and rw='0' ELSE
                            w1 WHEN current_state=idle and mem='1' and rw='1' ELSE
                            r2 WHEN current_state=r1 ELSE
                            w2 WHEN current_state=w1 ELSE
                            idle;
--
    PROCESS (clk150MHz) IS
    BEGIN
        IF rr='1' THEN
            current_state<=idle;
        ELSE
            If clk150MHz'event and clk150MHz='1' Then
                current_state<=next_state;
            End If;
        END IF;
    END PROCESS;
    ----------------------------------------------------------VGA Fifo write request
    WITH current_state select
            wrreq_fv <= '1' WHEN r2,
                          '0' WHEN OTHERS;
    ----------------------------------------------------------Write Enable and Output ENABLE
    WITH next_state select
            nWE_buf <= '1' WHEN r1 | r2 | idle,
                         '0' WHEN OTHERS;
        
    WITH next_state select    --
            nOE_buf <= '1' WHEN w1 | w2,
                         '0' WHEN OTHERS;
--
    PROCESS (clk150MHz) IS
    BEGIN
        IF rr='1' THEN
            nWE<='1';
            nOE<='1';
        ELSE
            If clk150MHz'event and clk150MHz='1' Then
                nWE<=nWE_buf;
                nOE<=nOE_buf;
            End If;
        END IF;
    END PROCESS;
    nWEout<=nWE;
    nOEout<=nOE;
    
    --Adreses OUT---------------------------------------
    WITH next_state select
            ADDR_val <= ADDR_read WHEN r1,
                          ADDR_write WHEN w1,
                            ADDR_reg WHEN OTHERS;
 
    PROCESS (clk150MHz) IS
    BEGIN
        IF rr='1' THEN
            ADDR_reg<=0;
        ELSE
            If clk150MHz'event and clk150MHz='1' Then
                ADDR_reg<=ADDR_val;
            End If;
        END IF;
    END PROCESS;
    ADDR<=conv_std_logic_vector(ADDR_reg, 18);
    
    --Adreses rw---------------------------------------    
    ADDR_read_temp<=0 WHEN current_state=r1 and ADDR_read=ram_max ELSE
            ADDR_read+1 WHEN current_state=r1 ELSE
            ADDR_read;
                                
    ADDR_write_temp<=0 WHEN current_state=w1 and ADDR_write=ram_max ELSE
            ADDR_write+1 WHEN current_state=w1 ELSE
            ADDR_write;
    
    PROCESS (clk150MHz) IS
    BEGIN
        IF rr='1' THEN
            ADDR_read<=0;
            ADDR_write<=0;
        ELSE
            IF clk150MHz'event and clk150MHz='1' THEN
                ADDR_read<=ADDR_read_temp;
                ADDR_write<=ADDR_write_temp;
            End If;
        END IF;
    END PROCESS;
    
    ADDR_read_out<=ADDR_read;
    ADDR_write_out<=ADDR_write;
    
    --Data----------------------------------------------------
    WITH current_state select
            DataIO <= "ZZZZZZZZZZZZZZZZ" WHEN r1 | r2,
                               Data_to_ram WHEN w1 | w2,    
                                         DataIO WHEN OTHERS;
    WITH current_state select
            Data_from_ram<= DataIO WHEN r2,
                        Data_from_ram WHEN OTHERS;
    ----------------------------------------------------------

have a look in the RTL viewer, or the post map viewer. follow the idle and r1 lines from the encoded SM register. see what they clock, because I cant see anything too suspicious from this code.

Hey,

latches are pretty bad. why have you used them? None of the code you posted should create latches.

Umm, for example, doesn't this create a latch?

WITH current_state select
            Data_from_ram<= DataIO WHEN r2,
                        Data_from_ram WHEN OTHERS;

If a signal retains its value then it implies memory and in this case a latch.

The code I posted is the only one containing anything related to SM or states.

WITH current_state select
            Data_from_ram<= DataIO WHEN r2,
                        Data_from_ram WHEN OTHERS;

WITH current_state select
            DataIO <= "ZZZZZZZZZZZZZZZZ" WHEN r1 | r2,
                               Data_to_ram WHEN w1 | w2,    
                                         DataIO WHEN OTHERS;

I didnt read it properly first time. The problem comes because you're connecting data_from_ram and DataIO to themselves when in certain states - this is where the latches come from. Latches are bad because you cannot analyse them with timing analyse and they are highly affected by temperature and subject to glitches.

Ok, didn't know that, thanks!