No PLL output on modelsim

ok that's weird. I used megawizard to create a pll block using Quartus 13.1. The top lines in the vhdl code are:

LIBRARY ieee;

USE ieee.std_logic_1164.all;

LIBRARY altera_mf;

USE altera_mf.all;

perhaps you should upgrade your quartus version. You don't need the subscription version, use the free one. I'll try doing the modelsim simulation as well.

Great. it works in modelsim.

I am driving inclk with 50Mhz, and the pll ratio is 5 to 1, so i expect a 250mhz clock out.

http://i.imgur.com/2qcwd6p.png

As you see in the wave plot, it takes the output about 80 ns before it is locked to 250mhz, till then it is unknown. That may be one of your problems - you aren't running the simulation long enough.

The inclk period is 20000ps as expected, and the c0 period is 4000ps also as expected.

Also I drive the reset signal high for the initial 40ns just to make sure everything starts from 0.