No Output from VHDL code !?

Hello,

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In your case, when you are converting integer, dont directly convert to std_logic_vector instead first convert either to signed or unsigned and then convert to std_logic_vector. please remember you are using std_logic_arith library.

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The suggestion is correct regarding std_logic_arith library, as the design also references std_logic_unsigned, all std_logic_vector is regarded as unsigned as well. Personally, I dislike std_logic_unsigned respecetively std_logic_signed cause you get difficulties when using signed and unsigned in combination and would do as you suggested. But the code creates well defined behaviour anyway.

Generally, with VHLD it's very unlikely that HDL compiler misunderstands your code and does something different to my opinion. With VHDL the compiler most likely complains about ambiguous types when you never would have thought of. So if the compiler accepts the code, you can be rather sure that no ambiguousities are left.

Regards,

Frank