No Output from VHDL code !?

Hello farrukh,

few things for your attention: you are using a clock in your design. But instead of a clock why you are using DigitValid instead of a clock? please have a look at that. Does your digitvalid signal is a clock?

Second, when you use conversion functions such as conv_integer or conv_std_logic_vector please dont forget to include respective library. In your case, when you are converting integer, dont directly convert to std_logic_vector instead first convert either to signed or unsigned and then convert to std_logic_vector. please remember you are using std_logic_arith library.

for better understanding please have a look at the following site for convertion functions:

http://dz.ee.ethz.ch/support/ic/vhdl/vhdlsources.en.html