Honored Contributor
Honored ContributorI've given him some suggestion cause he stated that is a newbie and a good starting in this world is very important in my opinion.
It must be clear that VHDL/Verilog is a different thing of all other programmer languages. Here you're describing what will be physicallly inferred. Stated this I try to answer about my suggestions. --- Quote Start --- Apart from confusing the author himself and project coworkers, which effect would you expect particularly from superfluous sensitivity list members. I assume - none. --- Quote End --- Code styling is not superfluous and moreover some "stupid" compilers will do a check for each signal in the sensitivity list and route the not used signal to the block also if not used. Apart that no issue (but in a congestionated design the route of useless signals must be prevent. --- Quote Start --- Which purpose does it serve, except from making the code less readable? I regard it a valuable feature of HDL compilers, that they are able to infer certain structures, including multipliers and memory from HDL code and generally try to utilize it for compact, functional code. --- Quote End --- The code will maybe become less readable but you've more control on the timings, moreover you've to understand what it's happening and that's not the feelings I've reading that code. I explain write a "*" and a "/" in VHDL mean inferr HARDWARE multiplicators and divisors that are a lot of logic cell (or hw dedicated cells) and their timings should be critical expecially if not in a synchronous process as this one. Imo in writing VHDL, you must take in account all you're doing and what the compiler shall syntetize else when you'll download the code on an HW and it doesn't work you don't know what to look at.
