No Output from VHDL code !?

Since you're a newbie I give you some suggestions.

First of all NEVER use in VHDL signal such as integers, but use always standard_logic_vector.

Moreover in a sequential process try to use only the Reset and the Clock in the sensitivity list.

All other signals must be clocked (pay attention that they're correctedly clocked among different clock domains).

In your code here you've specified also a clock in the sensitivity list but never used it in the code, remove it from the sensitivity list of the process.

Remember that a "*" is an hardware multiplication, so pay attention to timings.

It'll be better if you not use the "*" but that you define the hardware multiplicator and then specify its input and output taking into accout the latency it haves (ofc use a clocked one version).

Hope that it could be of use for your future.

Best regards