No messages in Modelsim [waveview & messageviewer]

I just tried this small example

entity top is
end;
library IEEE;
    use IEEE.std_logic_1164.all;
architecture arch of top is
begin
  process
    begin
      wait for 1 ns;
      report "message 1";
      wait for 1 ns;
      report "message 2";
      wait for 1 ns;
      wait;
    end process;
end;

vlib work
vcom report.vhd
vsim -i top -msgmode both -do "run -all"

 //  Questa Sim#  //  Version 10.2a win32 Mar 15 2013#  //#  //  Copyright 1991-2013 Mentor Graphics Corporation#  //  All Rights Reserved.#  //#  //  THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION#  //  WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS#  //  LICENSORS AND IS SUBJECT TO LICENSE TERMS.#  //#  vsim -do {run -all} -i -msgmode both top #  Loading std.standard#  Loading std.textio(body)#  Loading ieee.std_logic_1164(body)#  Loading work.top(arch)#1#  run -all #  ** Note: message 1#     Time: 1 ns  Iteration: 0  Instance: /top#  ** Note: message 2#     Time: 2 ns  Iteration: 0  Instance: /top

Update: I have searched the great world wide web far and wide, but haven't found a solution, or a companion in misfortune. I'll keep searching and trying. But isn't there anyone who could point me in the right direction?

Are you using command line switches -msgmode or -displaymsgmode?

yup, I do. I have them in a .do file after compilation of the files, and before the running of the simulation. I see the reports being "executed" as they appear in the transcript.

Well, it has been a while, but I still have not found a solution. Is there someone with a creative idea that might work?

Instead of using switches, try setting the variables in the modelsim.ini file

done that, no changes. As said before, I do see them in my transcript, but not even a hint in the waveform or messageviewer. Also there are no filters on the messages.

Are you talking about Tcl script output?

puts and echo are no problem, what I mean is the following:

report "clockgen: started loop" severity note;

# ** Note: clockgen: started loop#     Time: 10 ns  Iteration: 0  Instance: /testbenchfile

This works fine.

vlib work
vcom C:/altera/13.0sp1/report.vhd
#  Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov  2 2012
#  -- Loading package STANDARD
#  -- Compiling entity top
#  -- Loading package TEXTIO
#  -- Loading package std_logic_1164
#  -- Compiling architecture arch of top
vsim -i top -msgmode both - -do "run -all"
#  ** Error: (vish-3296) Unknown option '-'.
#  Use the -help option for complete vsim usage.
#  Error loading design
vsim -i top -msgmode both -do "run -all"
#  vsim -do {run -all} -i -msgmode both top 
#  Loading std.standard
#  Loading std.textio(body)
#  Loading ieee.std_logic_1164(body)
#  Loading work.top(arch)
#  run -all 
#  ** Note: message 1
#     Time: 1 ns  Iteration: 0  Instance: /top
#  ** Note: message 2
#     Time: 2 ns  Iteration: 0  Instance: /top