Nios2 Flash Programmer in Quartus II v11 sp1

Ok, I've done some more digging, and it would appear to be a problem with Qsys and tristate bridges.

The original v9 design in SOPC builder was imported into Qsys and "upgraded" to Qsys. This did various things, including changing to a tri state conduit bridge and a tri state conduit pin sharer. The Pin sharer is set up correctly, and shows 21 output address lines, 8 bidirectional data lines and 4 output control signals (ce_n to sram and flash, and oe_n and we_n). Although at this point the only bidirectional signals are the data pins, when it generates the Qsys system the top level entity has bidirectional pins for address, data, ce_n, oe_n and we_n. It also decides to make them all vectors but that seemed ok.

Having checked the fitter messages more carefully, it implies that the output enable for ce_n, oe_n and we_n are always disabled. But I never put those in, so how can I persuade Qsys to enable them? I'm starting to pull my hair out here!

Any clues gratefully received.

Cheers,

Simon

It comes from using the VHDL Example template from Qsys - this has the ce, oe, we signals as vectors(0..0) but they aren't vectors in the Verilog module it generates. This means the two sets of signals don't connect. If you change the component declaration in your top-level file to have std_logic, rather than std_logic_vector then it all hooks up properly.

I found the answer somewhere else on this forum, but can't remember exactly where.