Nios2 Flash Programmer in Quartus II v11 sp1

It comes from using the VHDL Example template from Qsys - this has the ce, oe, we signals as vectors(0..0) but they aren't vectors in the Verilog module it generates. This means the two sets of signals don't connect. If you change the component declaration in your top-level file to have std_logic, rather than std_logic_vector then it all hooks up properly.