Honored Contributor
Honored ContributorOk, I've done some more digging, and it would appear to be a problem with Qsys and tristate bridges.
The original v9 design in SOPC builder was imported into Qsys and "upgraded" to Qsys. This did various things, including changing to a tri state conduit bridge and a tri state conduit pin sharer. The Pin sharer is set up correctly, and shows 21 output address lines, 8 bidirectional data lines and 4 output control signals (ce_n to sram and flash, and oe_n and we_n). Although at this point the only bidirectional signals are the data pins, when it generates the Qsys system the top level entity has bidirectional pins for address, data, ce_n, oe_n and we_n. It also decides to make them all vectors but that seemed ok. Having checked the fitter messages more carefully, it implies that the output enable for ce_n, oe_n and we_n are always disabled. But I never put those in, so how can I persuade Qsys to enable them? I'm starting to pull my hair out here! Any clues gratefully received. Cheers, Simon
