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Asifa's avatar
Asifa
Icon for New Contributor rankNew Contributor
11 months ago

NIOS ii/e clock frequency differ from real-time running frequency.

I have created a Qsys circuit using Nios II/e, with a clock frequency of 50 MHz. Other peripherals are also connected, as shown in the attached photo. I wrote a program in Eclipse, and when I checked...
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sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
11 months ago

The names don't seem to match (clk_clk in Pin Planner vs. clk_clk_in from the exported interface column in PD). Go to the Generate menu in PD and select Show Instantiation Template (even though you are not instantiating the system) to verify that the name for the signal is correct.

Also, instead of relying on a signal level for testing this in your code, you may want to count clock ticks in the processor (nticks). Nios software development documentation can help with this.

Asifa's avatar
Asifa
Icon for New Contributor rankNew Contributor
11 months ago

The name of the signal is correct. I have attached the Instantiation template picture of PD. And still, I am struggling with the low clock speed toggling of the GPIO pins.