Forum Discussion
Asifa
New Contributor
New ContributorNIOS ii/e clock frequency differ from real-time running frequency.
I have created a Qsys circuit using Nios II/e, with a clock frequency of 50 MHz. Other peripherals are also connected, as shown in the attached photo. I wrote a program in Eclipse, and when I checked...
sstrell
Super Contributor
Super ContributorOK, so you have a top-level clock pin named clk_clk on pin AF14. Is that connected in your design somewhere to the clk_in interface of the Platform Designer system? Do you have a top-level design that instantiates the PD system or is the PD system itself your top-level design for the project?
AsifaYes, the clk_in interface is connected to the platform designer I have attached a screenshot of that. My PD system is itself my top-level design for the project.
