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Asifa's avatar
Asifa
Icon for New Contributor rankNew Contributor
11 months ago

NIOS ii/e clock frequency differ from real-time running frequency.

I have created a Qsys circuit using Nios II/e, with a clock frequency of 50 MHz. Other peripherals are also connected, as shown in the attached photo. I wrote a program in Eclipse, and when I checked...
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tehjingy_Altera's avatar
tehjingy_Altera
Icon for Regular Contributor rankRegular Contributor
11 months ago

Hi Asifa


Happy New Year!

Usually in a board there will be clock circuity that will supply different clock output to the board.

A clock output will be connected to the FPGA. You would need to fin that pin that the clock is connected to and in the Quartus Pin Planner define that the pin the clock is connected to.


Regards

Jingyang, Teh


Asifa's avatar
Asifa
Icon for New Contributor rankNew Contributor
11 months ago

Hello Happy New Year,

I have added a screenshot of the PIN planner showing the clock I selected and a photo from the manual, which mentions 50 MHz. Could you please help me identify the issue?