Forum Discussion
Asifa
New Contributor
New ContributorNIOS ii/e clock frequency differ from real-time running frequency.
I have created a Qsys circuit using Nios II/e, with a clock frequency of 50 MHz. Other peripherals are also connected, as shown in the attached photo. I wrote a program in Eclipse, and when I checked...
AsifaNew Contributor
New ContributorI am only working with GPIO pins; I have not attached any extra hardware to the FPGA (Cyclone V). Sorry, I am not getting your point. How do I provide a clock source on the hardware (FPGA)? I have also attached a part of the code to check if it’s a coding problem.
sstrell
Super Contributor
Super ContributorOK, on your board (is it a custom board or a development kit?), you have a clock signal going into clock pin(s) on the FPGA coming from, typically, a clock oscillator or crystal. What is that clock source and can you verify that it is providing the 50 MHz clock to the FPGA device that you expect?
Just because you are working on some GPIO signals doesn't mean you can ignore the overall design of the FPGA, including how it is clocked.
