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Altera_Forum's avatar
Altera_Forum
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15 years ago

Nios-controlled LUT

Hello

I am tryingo to implement a very simple system: there is a LUT made up in vhdl (using the case statement), and I would like to modifyLUT's coefficients using a Nios2 processor.

The lut is something like this

--- Quote Start ---

alway@(posedge clock)

case (data_in)

8'd0 : data_out=0;

8'd1 : data_out=1;

8'd2 : data_out=2;

...and so on;

endcase

--- Quote End ---

with more case and inserted in a module.

I would like to be able to update the values, instead having 0,1,2...

But i really don't have many ideas on how to do that.

I thought that I could use a small ram block, or a fifo between the Nios master and the custom block, but I don't know if it could be a good idea.

Could anyone give me any hint, or any suggestions?

best regards

Phate.

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    I would make those 0, 1, 2 values inputs into your module and then drive them using a PIO from SOPC Builder. The PIO is memory mapped so Nios II can write to it using a memory write operation. You could use a single PIO for all three values if they don't need to be wide or use three separate PIOs.

    If you take a look at the Nios II design examples you'll find a bunch of them that use PIOs to drive values out to pins connected to LEDs. Instead of driving pins you would drive the signals into your own module.

    Now with all that said if you have a big lookup table with many cases to evaluate I would use an onchip memory for this. One port of the onchip memory you could use an Avalon-MM slave port and the other port would have 'data_in' connected to the address port. The output from the second port would connect to 'data_out'. This is a more logic efficient method and it should hit a much higher clock frequency too.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Thanks for your reply guys.

    Today I will try to use the suggestion given by Bad Omen, running an onchip ram trough an Avalon memory-mapped-bus.

    I hope it won't be too difficult.