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Altera_Forum's avatar
Altera_Forum
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11 years ago

Newbie TCl scripting

Dear all,

I'm a begineer in scripting and also don't know if this is the way to go.

I have a design in Quartus (10.1sp1) (described in HDL, no NIOS).

The timing constraints are defined in a .sdc file.

I would like to 'Compile' with decreasing clock period (10ns 9.9ns 9.8ns etc.) to reach the timing limit of the design.

Is ther a way to automate this process and write on a file the limit clock period?

I'm thinking of a script that can be run from command line (DOS window) or in the 'TCL window'?

Thanks in advance for any tip.

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Take a look at the Tcl script I wrote for the Arria V Transceiver Toolkit example

    https://www.ovro.caltech.edu/~dwh/correlator/cobra_docs.html

    I'm pretty sure there is a loop that runs through the various PHYs and runs the synthesis for each one. If its not in there, I might be thinking of another example ... either way, the Tcl is nice, so you'll be able to figure it out. If not, ask, and I'll give you some suggestions.

    10ns clock period is only 100MHz. If you cannot meet that with HDL code, chances are you have bad code. Rather than try to tweak the clock period, you should look at the top failing paths and see if the code in that path can be improved, eg., by cutting paths with registers (pipelining your logic).

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Thank you for your info.

    I'll give a look to the website and let you know.