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Altera_Forum's avatar
Altera_Forum
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13 years ago

Never ending compilation, implosion of Quartus Map, compilation in modelsim works

Hi,

I have an intresting issue with my VHDL code which I attached with some comments(logic3.vhd is the newest version).

When compiling the code in quartus( I've tried versions 12sp2, 10.1 and 9.0 and on a different computer) for a width of generic n more than about 10 my code won't stop compiling. During this time, the quartus_map process just implodes taking up more and more RAM(up to about 4Gb) after which it quits, cancelling the compilation. I've narrowed the problem down to 2 lines of code I outlined in the attached file but I can't seem to solve the problem(I've tried many coversions etc etc).

The weirdest part is the code compiles PERFECTLY fine in modelsim(with n widths up to 1000) and it gives me correct results(the code generates primitive polynomials), so I am at a complete loss as i can't pinpoint the problem.

I've also had this problem with an older version of the code (logic.vhd which also requires bilbio.vhd) with it compilating in modelsim and having correct outputs. The problem in this older version was even weirder, as the difference in compiling at all had to due with a value "10"(which didn't work) and all other values("01","00","11"-I've outlined this in the code) compile just perfectly fine, this is definitely the weirdest problem I've every had in any programming(values having any difference on complication of code???).

I need to compile this to finish my project with n being about 1000, haven't been able to find a solution since a week, please help.

Fred

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Reviewing the resource utilization with small n values reveals the huge logic effort and at least 2^n algorithm complexity. So it's clear that code can't be imlemented in FPGA hardware for n values above 10, 12 or so.

    Functional simulation with Modelsim takes a different approach, it interpretes the code sequentially, stepping through the iteration loops. Thus it has less problems to deal with algorithm complexity, at cost of simulation time.

    The problem might be possibly solved using sequential rather than parallel processing. This means to replace the iteration loops by clocked state machines.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    That seems to make sense, I don't have much expierience in VHDL and used a programming style similar to C,C++ etc. It seems like I will have to implement most of the functions as clocked state machines.

    Thanks for the help.

    Fred