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Altera_Forum
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13 years ago

Never ending compilation, implosion of Quartus Map, compilation in modelsim works

Hi, I have an intresting issue with my VHDL code which I attached with some comments(logic3.vhd is the newest version). When compiling the code in quartus( I've tried versions 12sp2, 10.1 and...
Altera_Forum's avatar
Altera_Forum
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13 years ago

That seems to make sense, I don't have much expierience in VHDL and used a programming style similar to C,C++ etc. It seems like I will have to implement most of the functions as clocked state machines.

Thanks for the help.

Fred