Never ending compilation, implosion of Quartus Map, compilation in modelsim works

Reviewing the resource utilization with small n values reveals the huge logic effort and at least 2^n algorithm complexity. So it's clear that code can't be imlemented in FPGA hardware for n values above 10, 12 or so.

Functional simulation with Modelsim takes a different approach, it interpretes the code sequentially, stepping through the iteration loops. Thus it has less problems to deal with algorithm complexity, at cost of simulation time.

The problem might be possibly solved using sequential rather than parallel processing. This means to replace the iteration loops by clocked state machines.