Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Need to constrain write enables to FIFO

We have a design that is not meeting timing in Quartus / TimeQuest. Basically, we have a dual-clock FIFO that has a fast write clock and a slow read clock. The write enable signal to the FIFO only occurs every fourth write clock. But, TimeQuest is assuming that a FIFO write can occur every write clock causing timing to not close. The FIFO is implemented in an MLAB and the timing errors occur on the FIFO's write address internal generation. How do we generate a constraint (maybe multicycle on the FIFO write data?) to define the write enable only occuring every fourth clock? Thanks for your help.

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    You're saying your external write signal only pulses once every 4 clock cycles. Is the data valid four clock cycles before that pulse, i.e. it changes every four cycles alongside the write enable? If not, you can't multicycle. (I think, I'm writing this rather quickly before...) If the data and address are stable for four clock cycles, then you can add a multicycle:

    set_multicycle_path -setup -from {data_regs[*]} -to {*fifo*} 4

    set_multicycle_path -hold -from {data_regs[*]} -to {*fifo*} 3

    I believe you can do something similar with the address(and if the WE is every 4 cycles, then the address should update every 4.) If they're failing, just look at the names in the failing paths. If they're not, then do some report_timing -npaths 1000 -pairs_only -to *fifo_name* -panel_name fifo_paths, and just look around to find them. Shouldn't be too hard. (And you can locate them to the Technology Map viewer to make sure they really drive the RAM.) Technically, if they're making timing you may just leave them single cycle, as it probably doesn't help much to MC them.