Need to constrain write enables to FIFO

You're saying your external write signal only pulses once every 4 clock cycles. Is the data valid four clock cycles before that pulse, i.e. it changes every four cycles alongside the write enable? If not, you can't multicycle. (I think, I'm writing this rather quickly before...) If the data and address are stable for four clock cycles, then you can add a multicycle:

set_multicycle_path -setup -from {data_regs[*]} -to {*fifo*} 4

set_multicycle_path -hold -from {data_regs[*]} -to {*fifo*} 3

I believe you can do something similar with the address(and if the WE is every 4 cycles, then the address should update every 4.) If they're failing, just look at the names in the failing paths. If they're not, then do some report_timing -npaths 1000 -pairs_only -to *fifo_name* -panel_name fifo_paths, and just look around to find them. Shouldn't be too hard. (And you can locate them to the Technology Map viewer to make sure they really drive the RAM.) Technically, if they're making timing you may just leave them single cycle, as it probably doesn't help much to MC them.