Need some help

Hey could someone help me and fix the problem , i can't find where i made the mistake , i'm new to this...

library ieee;

use ieee.std_logic_1164.all;

entity sck is

port (

i_bit0 : in std_logic_vector(1 downto 0);

o_bit1 : in std_logic_vector(1 downto 0);

o_bit2 : out std_logic_vector(5 downto 0));

);

end sck;

architecture behavioral of sck is

signal A: std_logic_vector(5 downto 0);

begin

A<= o_bit1 and o_bit2;

process (A)

begin

case i_bit0

when "00" => A <="011100";

when "01" => A <="101010";

when "10" => A <="110011";

when "11" => A <="111111";

when others => null;

end case;

end process;

end behavioral;