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Honored Contributor
Honored ContributorNeed help with VHDL!!! =(
Hi everyone. I've been trying to fix this code but failed. Can anyone tell me what's wrong with it?
Also, what does this mean? What's the relation between them?buf(serial_count) := serial_in_port;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity MetroLRT is
port(
clk: in bit;
rst: in bit;
task: in bit_vector(1 downto 0);
stationed: in bit_vector(3 downto 0);
timeSTP: in bit;
serial_in_port: buffer std_logic;
serial_out_port: out bit;
gate_open_out: out bit
);
end MetroLRT;
architecture rtl of MetroLRT is
--signal
signal header1: std_logic_vector(3 downto 0);
signal balance1: std_logic_vector(6 downto 0);
signal t_stamp1: std_logic;
signal card_in1: std_logic_vector(15 downto 0);
signal station1: std_logic_vector(3 downto 0);
signal serial_count: bit;
signal buf: bit;
begin
process(clk, serial_in_port)
--variable
begin
if rst = '0' then
serial_in_port <= '0';
elsif
clk'event and clk = '1' then
if serial_in_port <= '1' then
buf(serial_count) := serial_in_port;
--store card info to all temporary variables
card_in1 <= "0000000000000000";
header1 <= "1010";
t_stamp1 <= '1';
station1 <= "0000";
end if;
end if;
end process;
enter_station: process(task)
begin
if task = "00" then
if header1 = "1010" then
if balance1 >= "0001000" then
if t_stamp1 = '1' then
card_in1 <= "0000000";
station1 <= "0000";
gate_open_out <= '1';
else
card_in1 <= null;
station1 <= null;
gate_open_out <= '0';
end if;
end if;
end if;
end if;
end process;
end rtl;
