Need help with VHDL!!! =(

Hello Jigalong; I have modified your code below to be a bit cleaner and address the issue that mazel mentioned above, as well as remove the "null" statements which are not valid & change to VHDL 2008. This is a good illustration of some of the basic constructs that make 2008 a bit cleaner. -James

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity MetroLRT is

port(

clk: in bit;

rst: in bit;

task: in bit_vector(1 downto 0);

stationed: in bit_vector(3 downto 0);

timeSTP: in bit;

serial_in_port: buffer std_logic;

serial_out_port: out bit;

gate_open_out: out bit

);

end MetroLRT;

architecture rtl of MetroLRT is

--signal

signal header1: std_logic_vector(3 downto 0);

signal balance1: std_logic_vector(6 downto 0);

signal t_stamp1: std_logic;

signal card_in1: std_logic_vector(15 downto 0);

signal station1: std_logic_vector(3 downto 0);

signal serial_count: bit;

signal buf: std_logic;

begin

process(all)

--variable

begin

if not(rst) then

serial_in_port <= '0';

elsif rising_edge(clk) then

if serial_in_port then

buf <= serial_in_port;

--store card info to all temporary variables

card_in1 <= X"0000" ;

header1 <= X"A";

t_stamp1 <= '1';

station1 <= X"0";

end if;

end if;

end process;

enter_station: process(all)

begin

if task = "00" then

if header1 = "1010" then

if balance1 >= "0001000" then

if t_stamp1 = '1' then

card_in1 <= X"0000";

station1 <= "0000";

gate_open_out <= '1';

else

gate_open_out <= '0';

end if;

end if;

end if;

end if;

end process;

end rtl;