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Altera_Forum
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14 years ago

Need a help: genetic algorithm (GA) in a cyclone

Hello everyone. I'm beginner at the fpga development and sorry for my trite questions.

I have a big interest in the implementing GA in a fpga (it might be cyclone 2 or cyclone 3). Currently, I'm reading about configuration and i've found out that i have to work with an SRAM Object File (.sof) or a Programmer Object File (.pof).

question#1: where can i find the structure these files (some guide about these files)? Cause i have to manipulate the LUT and it's interconnection.

I'm going to use a JTAG configuration.

question#2: is it need to use another configuration files like a Jam File (.jam) or a Jam Byte Code File (.jbc) for configuration?

question#3: If anybody knows more simple way for manipulate the LUT and it's interconnection, please let me know.

Beforehand, many thanks to everyone for paying attention to my topic.

14 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    AFAIK sof and pof files are proprietary and their format isn't publicly available. You need to go through the Quartus synthesizer to generate/modify them.

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I'm going to develop an application that changes NETLIST file (.edf or .eco, or even .sof), uploads modificated file to the fpga and it should work. First of all, i'm trying figure out, what file i have to modify. Eventually, I even think about sending questions to altera support.

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I don't think anyone ever tried what you are describing, this is really non standard. It could be much easier to have your algorithm generate vhdl/verilog code and use the whole synthesizer imho.

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Thanks for the idea, may be i will use it. But i've got addition questions:

    # 1: Can we use a Technology-Specific Netlist (edf, edif or vqm) files instead of sof for manipulating logic elements?

    # 2: Does VPR 5 support altera device ?

    i figured out that the Berkeley Logic Interchange Format (blif) is suitable for evolving in GA. But unfortunately Quartus doesn't support it. And i found tools VPR 5 and T-VPACK, that work with blif, but i actually don't know, if VPR 5 and T-VPACK supports (can configure) altera device. Or it's need to use both VPR 5 and Quartus, converting from blif file to vqm/edf by VPR/T-VPACK and compiling to sof/pof by Quartus.

    Can you comment this idea? :)

    Thanks for help
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I would be surprised if Altera or Xilinx allow you to program their chips in anything other than their own format.

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    --- Quote Start ---

    I would be surprised if Altera or Xilinx allow you to program their chips in anything other than their own format.

    --- Quote End ---

    unfortunately, I have to agree with you. but i hope to program it in netlist level.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    The netlist level is pre-fit (or pre-assembler), so you would still have to re-run the fitter and assembler.